Conventional integrated circuit (IC) design is a resource-intensive and time-consuming process. Customization is one technique to streamline integrated circuit design. Customization refers to altering a standard base die design to enable particular base die functions. The base die typically includes all of the major resources to implement a particular function. The metal layers and vias connecting pads on the base die and core circuitry of the base die can be altered (i.e., customized) to provide certain input and output functions on the package pins.
Conventional integrated circuit design, including customization, is performed manually by a team of engineers. Unfortunately, the manual design of integrated circuits is very time consuming. FIG. 1 illustrates a conventional chip design process. The conventional chip design process may be divided into two phases: one phase generally occurs at the customer site, and another phase typically occurs at one or more design and testing sites. At the customer site, a field application engineer (FAE) meets with the customer to determine the customer's chip requirements. The field application engineer works with the customer to develop an initial pin layout. The initial pin layout is often dictated by the customer. However, the initial pin layout is subject to change, and often changes, due to later verification and validation operations which may determine that the initial pin layout fails to meet functional objectives or fails to comply with physical bonding rules.
After the customer and field application engineer develop the initial pin layout, the field engineer takes the initial pin layout to the design site. At the design site, the design engineer analyzes the initial pin layout to determine if the initial pin layout is a viable pin layout. If it is not, then the field application engineer resumes communication with the customer to propose another pin layout. Depending on the success in defining a pin layout that works for the customer and is viable for production, the field application engineer and customer may have to repeat this process several times to refine the customer's requirements and redesign the pin layout.
After a viable pin layout is identified, the design engineer designs the core circuitry of the IC which connects to the input/output (I/O) pin layout. The design engineer may use various electronic design automation (EDA) tools for circuit design, simulation, verification, logic synthesis, and placement and routing. Exemplary EDA tools are commercially available from companies such as Cadence, Synopsys, Mentor Graphics and Magma Design Automation. In one design methodology, a first step in the design of core circuitry of an integrated circuit is to convert the user specification into an abstract form of the desired circuit, for example, a register transfer level (RTL) description of the design. The RTL of the integrated circuit is assigned to core regions of the die and connected to the pin layout. The design engineer then performs logic synthesis in which the RTL is turned into a design implementation in terms of a gate level netlist. An EDA tool used by design engineers may illustrate input and output ports of a component, cell, or instance (also referred to as gates) with “pins” on their sides. These internal pins of various “gates” are connected together using interconnect traces. A net may be defined as a collection of electrically connected gate pins. As such, a list of the nets that specify the electrical interconnections between internal pins in an integrated circuit is referred to as a “netlist.” It should be noted that such “pins” interconnecting the internal components, or instances, on the die are to be distinguished from the external pins of a packaged device.
The next step in the integrated circuit design is the layout. The integrated circuit layout may be generated using the netlist or another description of the integrated circuit such as schematics, text files, hardware description languages, and so forth. For example, in a process referred to as placement and routing, a design engineer uses a netlist to produce the placement layout of the IC design. In placement, the gates in the netlist are assigned to non-overlapping locations on the die area. In routing, the wires (i.e., interconnect traces) that connect the gates in the netlist are added. The design engineer may perform layout verification using a technique referred to as design rule checking (DRC). If the layout violates design rules, then the designed IC may not function. The layout of the IC may be generated in a GDSII format (a database format which is commonly used in the IC industry for IC layout data exchange) and input to DRC software which generates a report of design rule violations. The GDSII files also may be used as the output of the IC design cycle that is provided to a foundry for fabrication of the IC.
At this stage in the design, the design engineer also may generate a schematic of the chip design. The design engineer also typically performs simulation and/or verification (e.g., timing and functional) to determine whether the IC design performs as intended using simulation tools, synthesis tools, and verification tools. Verification may also be referred to as a “Test Bench” which contains the descriptions of circuit stimuli and corresponding outputs which verify the behavior of the design over time. Script files may be generated by the design engineer to perform verification, for example, to run a static timing analysis (STA) of the designed IC, which may be performed to determine the expected timing of an IC without requiring simulation. While such timing measurements can be performed using circuit simulation, such an approach may be too slow to be practical.
The integrated circuit layout is then converted into mask layers (e.g., using GDSII files) for fabrication of wafers containing one or more of the designed integrated circuit dies. The integrated circuit dies then may be assembled into packaged components for prototype or commercial units. Once initial prototypes are built, the design engineer quickly performs measurements on the prototype to compare the prototypes' performance against expected results from their simulation tools. After prototypes have been tested, an engineer (e.g., the design engineer or a product engineer) conducts what is referred to as characterization to test the outer limits of the design to establish and/or verify the operational specifications for the design. A test engineer typically may generate the testing (e.g., wafer sorting) and characterization programs and hardware boards that are connected to a test system and used to test a particular IC die design. The test engineer also typically generates a schematic of the characterization and wafer hardware board in order to have such a board constructed to test the integrated circuit dies. An application engineer eventually generates a datasheet such as an I/O buffer information specification (IBIS) to describe the package parasitics and other package information. Any errors or mismatches identified by the design, test, and application engineers may be fixed through collaboration among the various engineers.
Although other conventional chip design processes may differ from the illustrated chip design process, the depicted chip design process is representative of the time and resources that are involved in producing a chip design and samples for a customer. Currently, in some types of chip development, a customer may expect a turnaround cycle time of about 10-15 weeks to produce samples. Additionally, chip design companies are limited in the number of chips that are produced because of the time and resource costs expended for each chip design. In other words, the repetitive design process in which a customer designs and redesigns an integrated circuit to accommodate the design guidelines imposed by the customer specification can delay the time in which a customer obtains commercial units of the integrated circuit and can limit the chip designers in their ability to produce more integrated circuit designs.